關於 solution architecture design ，我們在網路上蒐集到這些相關的討論、資訊與評價

【Demo Day 2020 精彩回顧 - WASAI Technology 】#Englishbelow
WASAI 提供絕佳的資料處理方案，他們的 FPGA 加速晶片平台以及相應優化的硬體架構，建構了一個大數據處理的加速引擎，比傳統的處理方法快六倍以上! 現在WASAI將攜著過人的數據處理技術進入了基因分析的領域，提出了一套具高精確性及穩定性的基因定序分析方法。

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WASAI, abbreviation for We Accelerate System Architecture & Infrastructure, offers a well-tailored solution for data processing. Its FPGA accelerator for Big Data Hadoop platform and optimized architectural design for Data Centers speed up keyword searching and key value sorting at 6x. Now WASAI enters the field of genomic analysis with its data processing power and provides an All-in-one DNA Sequencing Acceleration solution with high accuracy and consistency.

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Pets, pets, pets… 🐕‍🦺🐕🐩🐈❤❤
We love them and they love us. But why don’t they love our sofas?

Well, I’m sure they love couches. Just not in the same way that we do since they like to bite or scratch the most important piece of our living room furniture. And if you're stuck indoors with your pet, you might find that you are covered in just as much fur as them!

Your sofa is the heart of your home, and pets can be very territorial, so you'll have to decide if you want your pet on your sofa. As a pet lover like you do, I would want the best for my pets and at the same time, preserving the Center piece of my living room.

Best solution ➡️ Choosing the right sofa🛋🛋
At Flexis Haus, we provide furnitures 🪑🛋🛏sofas that are useful in homes with pets due to the proliferation of dust mites and bacteria in these animals.
Our collections are long-lasting, easy to maintain and most importantly - very pet-friendly💞

We hope this could be an enlightenment for you who are still looking for the right sofas while you

#stayathome with your pets👍
Wishing everyone #staysafe as well💪
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eCurve 1st floor Lot 127
Mutiara Damansara, 47810 PJ
Contact: 0192218272
Email: flexishaustrading@gmail.com
Website: www.flexishaus.com

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@ Flexis Haus

交通大學IBM中心特別邀請到ECE Department at New York University 的 Prof. H. Jonathan Chao 前來為我們演講，歡迎有興趣的老師與同學免費報名參加！

演講標題：CFR-RL: Traffic Engineering with Reinforcement Learning in SDN
演 講 者：Prof. H. Jonathan Chao (ECE Department at New York University)
時 間：2020/01/20(一) 15:00 ~ 17:00
地 點：交大工程四館816室
活動報名網址：https://forms.gle/k5txEfTX6jM7PBR98
聯絡方式：曾紫玲 Tel：03-5712121分機54599 Email：tzuling@nctu.edu.tw

Abstract:
Traffic Engineering (TE) is one of important network features for Software-Defined Networking (SDN) with an aim to help Internet Service Providers (ISPs) optimize network performance and resource utilization by configuring the routing across their backbone networks. Although TE solutions can achieve the optimal or near-optimal performance by rerouting as many flows as possible, they do not usually consider the negative impact, such as packet out of order, when frequently rerouting flows in the network. To mitigate the impact of network disturbance, one promising TE solution is forwarding the majority of traffic flows using Equal-Cost Multi-Path (ECMP) and selectively rerouting a few critical flows using SDN to balance link utilization of the network. However, critical flow rerouting is not trivial because the solution space for critical flow selection is immense. Moreover, it is impossible to design a heuristic algorithm for this problem based on fixed and simple rules, since rule-based heuristics are unable to adapt to the changes of the traffic matrix and network dynamics. In this talk, we describe a Reinforcement Learning (RL)-based scheme, called CFR-RL, that learns a policy to select critical flows for each given traffic matrix automatically. It then reroutes these selected critical flows to balance link utilization of the network by formulating and solving a simple Linear Programming (LP) problem. Extensive evaluations show that CFR-RL outperforms the best heuristic by 7.4% - 12.2% and reroutes only 10% - 21.3% of total traffic.

Biography:
H. Jonathan Chao is Professor of Electrical and Computer Engineering (ECE) at NYU, where he joined in January 1992. He is currently Director of High-Speed Networking Lab. He was Head of ECE Department from 2004-2014. He has been doing research in the areas of software defined networking, network function virtualization, datacenter networks, packet processing and switching, network security, and machine learning for networking. He holds 63 patents and has published more than 265 journal and conference papers. During 2000–2001, he was Co-Founder and CTO of Coree Networks, NJ, where he led a team to implement a multi-terabit router with carrier-class reliability. From 1985 to 1992, he was a Member of Technical Staff at Bellcore, where he was involved in network architecture designs and ASIC implementations, such as the world’s first SONET-like Framer chip, ATM Layer chip, Sequencer chip (the first chip handling packet scheduling), and ATM switch chip. He is a Fellow of National Academy of Inventors (NAI) for “having demonstrated a highly prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.” He is a Fellow of the IEEE for his contributions to the architecture and application of VLSI circuits in high-speed packet networks. He received Bellcore Excellence Award in 1987. He is a co-recipient of the 2001 Best Paper Award from the IEEE Transaction on Circuits and Systems for Video Technology. He coauthored three networking books. He worked for Telecommunication Lab in Taiwan from 1977 to 1981. He received his B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, Taiwan, in 1977 and 1980, respectively, and his Ph.D. degree in electrical engineering from The Ohio State University in 1985.