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verilog parameter array 在 Re: [問題] Verilog multi dimension arrays - 看板Electronics 的推薦與評價


作者sasako (模糊地讓我看不清)
看板Electronics
標題Re: [問題] Verilog multi dimension arrays
時間Tue Sep 28 01:35:00 2010

※ 引述《hardman1110 (笨小孩)》之銘言：
: 在一本verilog實務設計的書上有看到它支援多維陣列
: 請問這是可以合成的嗎?
: 我是否可以做以下宣告:
: reg [1:0]c[0:1];
: reg [1:0]a[0:1];
: reg [1:0]b[0:1];//都是寬度、大小為2的陣列
: 然後用for回圈assign
: c[i]<=a[i]+b[i];
: 我在工作站用system verilog compiler是可以過
: 但是用verdi看波形圖時，居然找不到a、b和c
: 可否請問各位先進小弟這個用法是否有誤，謝謝

最簡單的方法..

addr只有0跟1，就不要用陣列宣告囉！

嫌麻煩要改code

那就

wire [1:0]a0 = a[0];//for debug
wire [1:0]b0 = b[0];//for debug
wire [1:0]c0 = c[0];//for debug

反正到時候synthesis會幫你optimize...

這樣在Nwave上就可以拉a0,b0,c0訊號線出來..

--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 118.169.74.19
推 zxvc:可惜這作法治標不治本。如果維度不止這樣，就要展開很多。 09/28 06:11
→ zxvc:目前我見過最簡單dump MDA的方法是用VCS VCD+。ModelSim WLF 09/28 06:13
→ zxvc:也不難，但用它來debug似乎不太方便(我找不到reload waveform 09/28 06:14
→ zxvc:的功能)。 09/28 06:14
→ zxvc:至於用FSDB dump MDA難易度！？改天有空再試。 09/28 06:15
→ sasako:無所謂 維度太多 用c幫忙就可以了 重點是也不可能會很多... 09/30 03:05
→ sasako:太多乾脆用memory就行了.. 09/30 03:06
推 zxvc:用程式產生Verilog code有時也有缺點，要改陣列size，要重跑 09/30 06:36
→ zxvc:改程式/產生code/複製/貼上這個流程。Verilog/SystemVerilog 09/30 06:37
→ zxvc:只要把size參數化，改參數就行了。 09/30 06:38
→ zxvc:況且想要寫高度參數化的設計，MEM/MDA不可或缺，也許你不常用 09/30 06:40
→ zxvc:，但我就很常在用。我有個design就一堆2, 3D陣列。 09/30 06:41
推 zxvc:另外MEM/MDA不是只能用來寫memory，它還可以用來表示module 09/30 06:44
→ zxvc:所形成訊號的陣列。例如有個module，用loop generate產生 09/30 06:46
→ zxvc:產生module arrary，它的訊號用(MEM/MDA)arrarys表示就很適合 09/30 06:47
→ zxvc:。又如systolic design，這具有規律的硬體結構，也適合用 09/30 06:49
→ zxvc:陣列去表示。 09/30 06:50
推 zxvc:還有一點，用程式產生陣列展開的方法，整個HDL design的code 09/30 06:58
→ zxvc:會較多，較難維護。 09/30 06:59
→ zxvc:用Verilog/SystemVerilog本身支援的array去寫，code可以寫得 09/30 07:00
→ zxvc:很精簡，容易維護、要改容易改。 09/30 07:01
→ sasako:c也可以define 可以參數化 對我個人而言 很習慣這樣寫.. 09/30 22:24
→ sasako:在配合UltraEdit的編輯 很容易達成 ... 因為用你的方法 09/30 22:26
→ sasako:我還要去參考一些文件 且要擔心dump出來的東西太大 09/30 22:27
→ sasako:反正為了debug 讀進 寫出有沒有錯誤 覺得不需要太複雜 09/30 22:28
→ sasako:複製貼上 應該不用5秒鐘..重點只在於我想直接快速拉訊號線 09/30 22:30
→ sasako:作debug而已.. 09/30 22:30
→ sasako:假如我今天要把他做成IP來使用 才會去把所東西參數化 09/30 22:31
→ sasako:且公司會有很多design rule需要遵循 SystemVerilog就是不行 09/30 22:41
→ sasako:作為design的使用的語言 不過可以運用在驗證model pattern 09/30 22:42
→ sasako:或許你以後適合驗證 畢竟這種人比designer還少.. 09/30 22:45
→ sasako:SystemVerilog的確是可以像C一樣 精簡code 但是公司很多 09/30 22:48
→ sasako:tool不吃他的語法 這樣作最後只是自己搞自己而已 09/30 22:49
→ sasako:作為designer要非常小心 寫你有把握的寫法 要確定他可以相 09/30 22:50
→ sasako:容於每套tool 不要讓後面的人難做... 09/30 22:51
→ sneak: 會較多，較難維護。 https://noxiv.com 08/13 19:04
→ sneak: 。又如systolic https://daxiv.com 09/17 22:58
→ sneak: 用程式產生Verilo https://noxiv.com 11/11 15:57
→ sneak: 用Verilog/Sy https://noxiv.com 01/04 22:13






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verilog parameter array 在 verilog - SystemVerilog: How to give different parameters to ... 的推薦與評價

If the values you want to override cannot be computed by a simple loop expression, you can use a parameter array. ... Verilog finite state ... ... <看更多>

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