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signed verilog 在 [問題] verilog的合成問題- 看板Electronics - 批踢踢實業坊 的推薦與評價


作者vaca1 (無聊人)
看板Electronics
標題[問題] verilog的合成問題
時間Mon Apr 23 23:53:03 2012

大家好~小弟雖然已經接觸verilog幾年~但還是很嫩

有個問題想問一下~

input [3:0] a,b;
output [3:0] c ;

assign c = a + b;

跟

input signed [3:0] a,b;
output signed [3:0] c ;

assign c = a + b;

這兩種寫法dc合出來會是不同的電路嗎..

寫過幾個電路，盡量都會避免用 signed的方式宣告，因為不清楚dc會合出什麼東西

但最近看別人的code發現他這樣寫..請問一下各位高手囉~~感恩

--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 1.169.176.41
→ lovepy:從結果來看 在這情況下 合出來的東西好像可以一樣 但實際上 04/24 08:07
→ lovepy:我想可能得看所使用的合成軟體 應該也會造成差異 我猜的= = 04/24 08:08
推 kevinztw:乘法器才有分有號與無號 04/24 18:49
→ vaca1:我剛才寫了一個signed的乘法器 dc合不出來.. 04/24 23:52
推 zxvc:有沒有錯誤訊息？我印像中可以合成啊。 04/25 04:34
→ vaca1:dc會當掉… 04/25 12:42
推 pikachu2005:沒試過input signed但有寫過output signed DC可以合過 04/25 13:39
推 zxvc:剛才試過了，input/output都加signed可以compile。DC版本為 04/28 12:11
→ zxvc:2010.03。 04/28 12:12
→ vaca1:我DC版本是2008 自己電腦灌ubuntu32的 04/28 13:57
→ vaca1:input [3:0] a,b; output [7:0] c; assign c=a*b; 04/28 13:58
→ vaca1:忘了寫 是signed的 input 跟 output 合的時候會當... 04/28 13:58
推 zxvc:幫你測過上述code，沒有問題。不知是你的DC哪設定不對。 04/28 16:06
→ uxijgil:加法沒差 DC雖然對待a.b為signed 但做法同unsigned 04/29 03:47
→ sneak: 0] c; assig https://noxiv.com 08/13 19:25
→ sneak: 乘法器才有分有號與無號 https://daxiv.com 09/17 23:19






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signed verilog 在 Understanding signed numbers in Verilog - Electrical ... 的推薦與評價

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signed verilog 在 [問題] verilog的合成問題 的推薦與評價

[問題]verilog的合成問題@electronics，共有16則留言，7人參與討論，5推0 ... 跟input signed [3:0] a,b;output signed [3:0] c ;assign c = a + b; ... ... <看更多>

signed verilog 在 32 bit multiplier verilog code github - Creative Design Bali 的推薦與評價

A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm - multiply. c. Multiply (that is - AND) each bit of one ... ... <看更多>

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A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm - multiply. c. Multiply (that is - AND) each bit of one ...

#95. Verilog $ signed（），这是什么？ - 堆栈内存溢出

我刚刚开始使用verilog。 我在看某人写的一个浮动乘法的一些示例代码，而我遇到了这个... 我只是想知道什么是signed。 我尝试使用谷歌搜索， ...

#96. Systemverilog real data type

The Apr 05, 2020 · Verilog Design Units – Data types and Syntax in Verilog. ... different data types in SV. parameter vs. int i // 2-state, 32-bit signed.

#97. Verilog HDL中的数值运算_符号_补码_应用 - 全网搜

在Verilog-2001标准中，除了整数类型之外，wire类型和reg类型以及模块的端口都可以用关键词signed定义为有符号类型，并且还可以应用系统函数$signed ...

#98. Verilog — 2001: A Guide to the New Features of the Verilog® ...

With Verilog-2001, signed operations can be performed with vectors of any size. For example: integer i, j; //signed 32-bit variables reg signed [63:0] m; ...

#99. Verilog HDL中的数值运算_符号_补码 - 手机搜狐网

在Verilog-2001标准中，除了整数类型之外，wire类型和reg类型以及模块的端口都可以用关键词signed定义为有符号类型，并且还可以应用系统函数$signed ...