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verilog signed 在 [問題] Verilog 有號數問題- 看板Electronics - 批踢踢實業坊 的推薦與評價


作者peliuya (偽美少女學園長)
看板Electronics
標題[問題] Verilog 有號數問題
時間Sun Dec 21 21:49:05 2008


我寫了一個計數器

reg [31:0] B1;
其數值在0~20000間計數。


還有一個有號數 ADC

reg signed [13:0] ADC;
其數值在-8192~8192間變化


另外有一個訊號線

wire [15:0] Duty;
assign Duty = ADC + 8192;
即使ADC加上一正值變為正數


輸出為PWM

output PWM
assign PWM = (B1 > Duty);
若計數器 B1 大於 Duty 時，則輸出為High。


但今天遇到一個問題：
若ADC為負值(ex: ADC = -1966)時，輸出訊號出現錯誤的情況，輸出全為Low。
若直接 assign Duty = (-1966)+8192; 則輸出訊號正確。


不知道為甚麼會發生這個情況，可否請板上先進不吝指導。


謝謝。

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※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.118.202.20
推 TroyLee:需要作 Sign Extension 嗎 12/21 23:06
推 keterwang:@@ ，不是只要射個threshold嗎 12/21 23:48
推 sasako:自己獨立寫個sign值運算的module吧... 12/22 01:36
→ colinshih:bit-length不同如何運算, 看一下書吧 你是化工系的吧? 12/22 01:37
→ peliuya:所以 sign 值的運算需要獨立建個 process囉？ 12/22 02:21
→ peliuya:我是電子系的 (掩面) 12/22 02:21
→ sasako:對我來說 我幾乎沒有宣告過reg signed這種東西 12/22 02:24
→ sasako:有所限制 詳細的只好看書 運算這種東西自己寫個module 12/22 02:26
→ sasako:很快 又不太容易錯.. 12/22 02:26
→ peliuya:可是因為我ADC是由輸入讀進來的…是2的補數… 12/22 02:27
→ peliuya:所以 如果不用signed 這個來放的話 應該會有錯吧？ 12/22 02:27
→ sasako:只要瞭解1's, 2's, sign magnitude 是如何運算 不難啦.. 12/22 02:28
→ sasako:告訴你 電路根本看不懂sign是啥小 不過就是人定的 12/22 02:29
→ sasako:電路只懂得01010.... 12/22 02:29
→ peliuya:還有想請問 我的寫法 問題是出在於？ 什麼觀念沒釐清？ 12/22 02:29
→ sasako:不管你暫存器存什麼 就是一堆0和1的東西.. 12/22 02:30
→ sasako:我只覺得有可能出現在sign這種宣告的用法 你使用錯誤而已 12/22 02:31
→ sasako:不然你可以試試看 不考慮sign的運算 然後跑跑看... 12/22 02:32
→ peliuya:不加sign 輸出也不對 畢竟放進去暫存器的代表數值就不同了 12/22 02:33
→ peliuya:跑模擬運算都很正常 可是接上板子實測就出問題了 = = 12/22 02:34
→ sasako:我覺得你還是明白我在說什麼 有些東西是人定的 12/22 02:36
→ peliuya:我想你的意思是另外建個process 對他做處理後再運算？ 12/22 02:37
推 sasako:那你明白我說電路只懂0101..的意思嗎？ 12/22 02:39
→ peliuya:了解 12/22 02:42
→ sasako:舉個簡單的例子 一般A+B 和 2's的A+B 演算法不同 12/22 02:42
→ peliuya:我只是不太懂 為甚麼ADC為正數時都正常 負數就出問題 12/22 02:43
→ sasako:那麼要如何告訴程式在作二補數運算 就是你的任務 12/22 02:44
→ peliuya:嗯 我再翻翻書嘗試看看 ^^ 12/22 02:46
→ sasako:你會用debussy作debug的話 就可以找到答案 12/22 02:48
→ peliuya:debussy？ 那是什麼？ 12/22 02:49
→ sasako:他可以看到每個時間點電路看到的值 12/22 02:50
→ sasako:寫verilog通常不是都用工作站 那是CIC提供的軟體壓 12/22 02:50
→ sasako:那是一套輔助設計者debug的工具 12/22 02:51
→ peliuya:我都只用xilinx ISE 寫一寫就直接在驗證版上 run (汗) 12/22 02:52
→ sasako:那你個design flow有點問題 應該都會在NCverilog環境寫好 12/22 02:53
→ sasako:在用debussy debug確定function正確 再燒到板子上 12/22 02:54
→ sasako:不然程式要是大一點 那你不就debug到死... 12/22 02:55
→ peliuya:是有用ISE本身的模擬軟體先跑看看時序 可是看起來很正常 12/22 02:58
→ peliuya:燒進去以後 卻不見得是這麼一回事 = = 12/22 02:58
→ sasako:那麼你看得到模擬每個時間點的值嗎？ 12/22 02:59
→ sasako:因為燒進去需要作合成 合成之後又要再次驗證function 12/22 03:01
→ peliuya:只能看到輸出入port的 所以我都把reg指定到輸出觀察 12/22 03:01
→ sasako:才會有pre-sim這種名詞存在 12/22 03:01
→ peliuya:合成的時候 也沒看到什麼奇怪的warning 12/22 03:02
→ peliuya:但是對這個不太懂 所以也不知道到底合成出什麼東西來 (汗) 12/22 03:03
→ sasako:所以你略過了RTL-sim這個過程..直接看pre-sim 12/22 03:03
→ peliuya:嗯 我不知道我的程式到底會做出什麼 RTL 12/22 03:04
→ sasako:沒有按照流程走出現問題也是應該的 你應該先確保RTL是OK的 12/22 03:04
→ sasako:不先確定RTL的function 只能說你賭得很大唷 12/22 03:06
→ peliuya:因為不是學這個的 就只看看書本的語法 直接下去寫 12/22 03:06
→ peliuya:實在是很慚愧 -__- 12/22 03:07
→ sasako:RTL指的是你原本未合成的code (應該知道吧！？) 12/22 03:07
→ sasako:但是你在訓練verilog 應該是要從tool開始.. 12/22 03:09
→ sasako:不然你以後找工作 跟你老闆說 你會寫 但你卻不跑RTL-sim 12/22 03:11
→ peliuya:看來我需要再多花點時間才行 感謝您的指導^^ 12/22 03:11
→ sasako:你真的需要在多花時間把基礎訓練好 加油 12/22 03:12
推 ksmrt0123:試試看 assign Duty = {ADC[13],ADC[13],ADC} + 8192; 12/22 03:22
→ peliuya:感謝樓上提供的方法^^ 順利解決這個問題 謝謝 12/22 22:14
推 TroyLee:其實這個問題就是我說得...Sign Extension 12/22 22:43
推 ksmrt0123: 這個問題就是T大說得..Sign Extension 12/23 00:11
推 ksmrt0123:還有原Po該謝的應該是T大跟熱心的sassako 12/23 00:19
→ peliuya:真的也很感謝T大和C大 十分熱心的指導我 謝謝！ 12/23 02:07
→ sneak: 電路只懂得01010. https://daxiv.com 11/11 14:54
→ sneak: 寫verilog通常不 https://yofuk.com 01/04 21:51






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And I also know how to describe following vhdl function into verilog function. entity MPY is. Port ( A : In std_logic_vector (23 downto 0);

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分类Verilog 教程 ... input signed [15:0] factor_real, // Wnr input signed [15:0] factor_imag, output valid, output signed [23:0] yp_real, //Xm+1(p)

#69. Signed serial-/parallel multiplication - Markus Nentwig

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm Summary A detailed discussion of bit-level trickstery in ...

#70. verilog sign과 unsign - 네이버 블로그

verilog sign 과 unsign ... Reg data type과 integer data type을 같이 사용하는 경우. ... intA = -4'd12 / 3; // expression result is 1431655761.

#71. Verilog HDL unsigned and signed operations ... - TitanWolf

Verilog HDL unsigned and signed operations. When performing arithmetic operations and assignments, it is important to pay attention to which operands are ...

#72. verilog的$signed - 程序员ITS401

有符号数和无符号数在计算机中的存储方式以及在Verilog中的运用（$signed函数）... #0.计算机组底层的电路只认识0和1，并没有...这里主要讨论无符号数和有符号数在 ...

#73. Verilog $signed(), what is this? - TipsForDev

There are a number of Verilog system functions can be used for synthesis as well as testbenches. Most of the synthesizable function perform some kind of ...

#74. verilog中$signed 能否综合 - 百度知道

综合工具只能综合你自己设计的东西，你这个东西是调用系统任务，也就是说调用别人的东西，不可能综合进去。 本回答被提问者和网友采纳.

#75. A Verilog parameter infers its type from its value — the myth ...

Because it's so common to assign a signed integer constant to a Verilog parameter parameter SIZE = 8; a myth has arisen that there is a ...

#76. SystemVerilog教程之Data Types Part-I - 知乎专栏

Introduction · SystemVerilog在Verilog的基础上添加了许多新数据类型， ... shortint: 16-bit signed integer. int :32-bit signed integer. longint ...

#77. 以Verilog 設計一個數位電路(11)--- unsigned , signed +

以Verilog 設計一個數位電路(11)--- unsigned , signed + *. 以Verilog 設計一個數位電路(11)--- unsigned , signed + *. Hex value: 35 × 76 = 186E

#78. Verilog 中的signed 和unsigned - 21ic电子技术论坛

1. verilog-2001 中添加了新的关键字signed，请问它是可综合的么？ 比如reg signed [7:0] a = -8'd10; 个人感觉貌似是不能的，寄存器只是存储二进制的数（ ...

#79. sign extension in verilog - Google Groups

I would like to design a 16 to 32-bit sign extension unit. I would ... sign's, how could I do this in verilog? rekz's profile photo ...

#80. 關於verilog中的signed類型

在Verilog-1995中，只有integer資料類型被轉移成有符號數，而reg和wire ... Verilog有兩個系統函數，$signed和$unsigned()，用以將括弧內的運算式轉換 ...

#81. 關於verilog-2001標准中signed類型的reg/wire - 开发者知识库

關於verilog中的signed類型. 在數字電路中，出於應用的需要，我們可以使用無符號數，即包括0及整數的集合；也可以使用有符號數，即包括0和正負數的 ...

#82. [問題] verilog的合成問題

[問題]verilog的合成問題@electronics，共有16則留言，7人參與討論，5推0 ... 跟input signed [3:0] a,b;output signed [3:0] c ;assign c = a + b; ...

#83. Verilog and SystemVerilog Gotchas: 101 Common Coding Errors ...

Synopsis: Unbased literal integers default to signed. Based literal integers default to unsigned. Literal integers in Verilog and SystemVerilog can be ...

#84. Signed arithmetic in Verilog | ASIC, FPGA and EDA reports

Verilog 1995, Signed * Signed module mult_signed_1995 (…

#85. l05.v

In Verilog or C: minus i = ~i + 1; // /// Two's Complement Sign Bit // // A ... Overflow Detection in Signed Addition // // There has been ...

#86. Systemverilog boolean type - CAL Sports Academy

Verilog Basics: Data Types, Operators, and Conditionals We will begin by ... 2's complement signed integer in arithmetic expressions, Default size is 32 ...

#87. 使用Verilog 設計CPU0 處理器 - 陳鍾誠的網站

Verilog 程式：cpu0s.v ... mdr, inout [31:0] dbus, output reg m_en, m_rw, output reg [1:0] m_size); reg signed [31:0] R [0:15]; reg [7:0] op; ...

#88. Verilog $ signed（），这是什么？ - 堆栈内存溢出

我刚刚开始使用verilog。 我在看某人写的一个浮动乘法的一些示例代码，而我遇到了这个... 我只是想知道什么是signed。 我尝试使用谷歌搜索， ...

#89. Verilog如何以負數表現？ - 優文庫 - UWENKU

//Declare the reg as signed and divide by a signed value reg signed [7:0] myReg; assign result = myReg/2; //Use system functions assign result = $signed(myReg)/ ...

#90. SystemVerilog for Design Second Edition: A Guide to Using ...

The first IEEE Verilog standard, Verilog-1995, had just one signed type, declared with the keyword integer. This type has a fixed size of 32 bits in most, ...

#91. The Verilog® Hardware Description Language

Conditional Isigned(m) Convert to signed $unsigned( Convert to m) unsigned Assign one of two values based on expression If the left operand is signed, ...

#92. Real Chip Design and Verification Using Verilog and VHDL

Using Verilog and VHDL 6.1 VHDL ARITHMETIC VHDL is a strongly typed language . Integer numbers are signed numbers , but unlike Verilog , represent a ...

#93. System Verilog Sine Function

Xilinx XST doesn't yet support those handy Verilog math functions, ... The input to this system is 17 bit angle in degrees (signed magnitude representation) ...

#94. SoC DV IP Verification - LinkedIn India

Experience of working in complex test-bench/model in Verilog, ... System Verilog, PLI/DPI interface, C/C , PERL/Shell script, ... You're signed out.

#95. Counter verilog - specialcourt.org

Verilog code for up counter: // FPGA projects using Verilog/ VHDL ... Signed values are not necessarily sign extended because the sign bit ...

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#97. [Verilog 踩雷部隊] Arithmetic right shift

是arithmetic right shift 在Verilog 裡的運算符號功能大概如下：. 4-bit: 0111 >>> 1 = 0011 4-bit: 1100 ... 因為要被算的數沒有指定為 signed

#98. Verilog有符號乘法：將不同大小的數字相乘？ - Tidewaterschool

乘以帶符號的數字時，verilog是否照顧輸入和輸出尺寸？ ... reg signed [31:0] a = -5; reg signed [63:0] b = 5; wire signed [63:0] c; assign c = a*b;.

#99. How to use Signed and Unsigned in VHDL - VHDLwhiz

The signed and unsigned types in VHDL are bit vectors which can be used in calculations. They overflow silently, and they get sign-extended ...