[ASML Recruiting] IC Design Engineer
The job is located in Hsinchu/Tainan that could work on the advanced analog and mixed signal ASIC for next generation electron detection channel for the leading edge e-beam inspection and metrology systems with work life balance.
The following are the Job Descriptions for this opportunity
• Develop the functional blocks of high-speed Analog-to-Digital Converter (ADC) and/or Phase-Locked Loop (PLL) in ASIC for the detection channel of electron beam inspection tools, including:
• Define the design specifications of the Read-Out Integrated Chip (ROIC) or chipset based on product roadmap and System Performance Specifications (SPS) defined by system engineer.
• Develop new circuit architecture and technical solutions for next generation ASICs in detection channel, including feasibility study, schematic design, pre-layout simulation, layout design, and post-layout simulation.
• Cooperate with Printed Circuit Board (PCB) designer to design Evaluation Board (EVB) and with test engineer to test and characterize the ASICs.
• Create Element Design Specifications (EDS) and Test Performance Specifications (TPS) based on detail ASIC design and chip test/verification.
• Cooperate with IC design partner to develop the ASICs for detection channel of of electron beam inspection tools, including:
• Review the detail schematic and layout design, TPS, and test results from our partner during the ASIC industrialization phase.
• Together with the engineering team from the partners, identify design solutions to achieve the specifications of the module/function. Review the design details and simulation results from our partner.
• Support module level and sub-system level integration
• Generate and / or review related IP documents
Provide with more information about the position: D&E - IC Design Engineer - Tainan/Hsinchu - Jobs | ASML
https://www.asml.com/en/careers/find-your-job/2/4/9/de-ic-design-engineer-tainanhsinchu-req24973
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phase locked loop 在 feversound.com Facebook 的最讚貼文
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一個鎖相環(PLL)是一個設計用於同步板子時脈與外部的時脈訊號的電路。鎖相環電路會比較外部訊號與電壓控制的石英震盪器(VCXO) ... ... <看更多>
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鎖相迴路(PLL: Phase-locked loops)是利用反馈(Feedback)控制原理实现的频率及相位的控制系統,其作用是将电路输出的信號与其外部的参考信號保持同步,当参考信號 ... ... <看更多>