That's a ternary operator. It's shorthand for an if statement. Format: condition ? if true : if false. Example: ... <看更多>

If you want to use the ternary (conditional) operator, you can use case equality ( === ) instead of logical equality ( == ): ... <看更多>

The following code does not compile in iverilog. I believe this is valid systemVerilog code. At least one commercial tool accepts this ... ... <看更多>