Either create the .f file dynamically as part of your build process, or use a Verilog file to do this instead. `ifdef ASIC `include ... ... <看更多>

verilog -modi-lookup: top_mac_ffsgpcs.v:596: Can't locate ``endif' module definition (Expanded macro to endif) ... <看更多>

There are no operations permitted in `ifdef , but the code you wrote is fine. You can get the effect of OR or AND operations by additional ... ... <看更多>

... <看更多>