... <看更多>

Here is an example which could work in some cases (works in synopsys vcs/system verilog). It generates an instance name per channel but in a ... ... <看更多>

The Verilog Standard does not impose a restriction on usage of whitespace characters. Quoting from the LRM: The macro text can be any arbitrary text ... ... <看更多>

But the Vunit parser doesn't allow this and issues warnings. In the verilog file below, the macro "MY_MACRO" is defined without spaces before ... ... <看更多>