but after simulation, i got the value 1'bx in u_a/u_sax/sb ;. how to convey the value "BRAM0" or "BRAM1" to the submodule parameter u_sax/sb ? ... <看更多>

Another issue are substrings, the same sintax as for the part of an array //. // test_string[i:j] is not legal in ncsim. //. // In ncsim the string method ... ... <看更多>

Join our Telegram group for more discussion and get some outstanding materials for exams and interview ... ... <看更多>

If you know it help me. Thanks. verilog · hdl · system-verilog · Share. ... <看更多>

VAST is a C++ library which represents Verilog in a recursive tree data ... std::string op_; : The string representation of the operation to perform (e.g., ... ... <看更多>